DRAM内存颗粒测试简介

IntroductiontoDRAMTesting---DRAMinsideteam---2015.MayAgendaBasisofTestingTypicalDRAMTestingFlowBurn-inDCTest(Open/Short,Leakage,IDD)FunctionalTest&TestPatternSpeedTestDRAMManufactureWaferAssemblyFinalTestingFinalProductWhyTesting?Toscreenoutdefect•Waferdefect•AssemblydefectMakesureproductmeetspecofcustomer•Voltageguardband•Temperatureguardband•Timingguardband•ComplextestpatternCollectdatafordesign&processimprovement•Quality•Reliability•Cost•EfficiencyICTestMethodologyICTesterPPSDriverComparatorDUT**DUT=DeviceUnderTestPowerSupplyOutputInputTestingofaDUT:1.ToconnectPPS,Driver,Comparator&GND.2.ToapplypowertoDUT.3.ToinputdatatoDUT(Address,ControlCommand,Data)4.Tocompareoutputwith“expectvalue”andjudgePASS/FAILBasicTestSignalDigitalWaveformElements•Logic•Voltage•TimingTypicalDRAMFinalTestFlowBurn-in•MBT(MonitorBurninTest):StresstoscreenoutEarlyFailures•TBT(TestBurninTest):Longtimepatterntest•VeryLowSpeed(5-20MHz),HighParallelTest(10-20Kpcs/oven),LowCostCoreTest•DCTest•FunctionalTest•LowSpeed(DDR3@667MHz),TypicaltesterAdvantestT5588+512DUTHiFixSpeedTest•Speed&ACTimingTest•FullSpeed(DDR3@1600MHzandabove),AdvantestT5503+256DUTHiFixBackend•MarkingBallScanVisualInspectionBakingVacuumPackDRAMBurn-in(MBT)MBTistostressICandscreenoutearlyfailuresHighTemperatureStress(125degC)HighVoltageStressStressfulPatternBIOperationTimeFailureRateInfantMortalityNormalLifeWornoutNewproductMatureproductBathCurveDRAMBurn-in(TBT)TBTisforlongtimetestpatternsMultipletemperaturetested(e.g.88’C,25’C,-10’C)LongtesttimeatlowspeedPatternscoverallcellarraysNoStressfulconditionHighparalleltestcount,lowcostBothMBTandTBTdoesNOTtestDC(AndoOven)DRAMAdvantestTest1.DCTestOpen/ShorttestLeakagetestIDDtest2.FunctionalTest(CoreTest)Differentparameter&PatternforeachfunctionTocheckDRAMcanoperatefunctionally3.SpeedTestTimingtest@differentspeedgradeDCTestDCTestMethod:a)ISVM:ISourceVMeasureb)VSIMVSourceIMeasureVCCVCCDCTest–OpenShortPurpose:•Checkconnectionbetweenpinsandtestfixture•CheckifpintopinisshortinICpackage•CheckifpintowaferpadhasopeninICpackage•Checkifprotectiondiodesworkondie•Itisaquickelectricalchecktodetermineifitissafetoapplypower•AlsocalledContinuityTestDCTest–OpenShortFailureMode:a)WaferProblemDefectofdiodeb)AssemblyProblemWirebondingSolderballc)ContactProblemSocketissueCoreCircuitDefectivediodeSocketPogoPindefectWiretouchedDCTest–OpenShortO/STestCondition:Procedure•Groundallpins(includingVDD)•UsingPMUforce100uA,onepinatatime•Measurevoltage•Failopentestifthevoltageisgreaterthan1.5V•Failshorttestifthevoltageislessthan0.2V100uA0.65VPMUforcesenseforceMeasureVss=0Vdd=0100uAFailOpenPassFailShort1.5V0.2VISVMOther=0Typical0.65VDCTest–OpenShortO/STestCondition:Procedure•Groundallpins(includingVDD)•UsingPMUforce–100uA,onepinatatime•Measurevoltage•Failopentestifthevoltageislessthan–1.5V•Failshorttestifthevoltageisgreaterthan–0.2VFailShortPassFailOpen–0.2V–1.5V-100uA-0.65VPMUforcesenseforceMeasureVss=0Vdd=0-100uAISVMOther=0Typical-0.65VDCTest–LeakagePurpose:•VerifyresistanceofpintoVDD/VSSishighenough•Verifyresistanceofpintopinsishighenough•IdentifyprocessprobleminCMOSdeviceDCTest–LeakageILIH/ILIL:InputLeakageHigh/Low•Toverifyinputbuffersofferahighresistance•NopreconditioningpatternappliedILOH/ILOL:OutputLeakageHigh/Low•Toverifytri-stateoutputbuffersofferahighresistanceinoffstate•Testrequirespreconditioningpattern•Performedonlyonthree-stateoutputsandbi-directionalpinsDCTest–LeakageFailureMode:a)Waferproblemb)Assemblyproblemc)SocketContactproblem(short)DiecrackBalltouch(Short)DCTest–InputLeakageLowTestCondition:Procedure•ApplyVDDmax(2.0V)•Pre-conditionallinputpinstologic‘1’(highvoltage)•UsingPMU(ParametricMeasureUnit)forceGroundtotestedpin•Waitfor1to5msec•Measurecurrentoftestedpin•FailIILtestifthecurrentislessthan–1.5uAPassFail–1.5uA0V-10nAPMUforceMeasureVss=0VDDmaxILILVLSICore“0”“1”allinputpins=2.3VOFFONDCTest–InputLeakageHighTestCondition:Procedure•ApplyVDDmax(2.0V)•Pre-conditionallinputpinstologic‘0’(Lowvoltage)•UsingPMUforceVDDMAXtotestedpin•Waitfor1to5msec•Measurecurrentoftestedpin•FailIIHtestifthecurrentisgreaterthan+1.5uAPassFail1.5uA2.0V10nAPMUforceMeasureVss=0VDDmaxILIHVLSICore“1”“0”allinputpins=0VONOFFDCTest–OutputLeakageLowTestCondition:Procedure•ApplyVDDmax(2.0V)•Pre-conditiontheDUTtotristatewithspecificpattern•Waitaspecifictime•UsingPMUforceVDDMAXtotestedI/Opin•Measurecurrent•FailIOHtestifthecurrentisgreaterthan+4.5uAorlessthan-4.5uAPassFailGT4.5uA0.0V-10nAPMUforceMeasureVss=0VDDmaxILOLVLSICoreOFFOFFPre-conditionPattern1/0FailLT-4.5uA“0”Allinputpins=2.3VAlloutputpins=0V/2.3VDCTest–OutputLeakageHighTestCondition:Procedure•ApplyVDDmax(2.0V)•Pre-conditiontheDUTtotristatewithspecificpattern•Waitaspecifictime•UsingPMUforceVDDMAXtotestedI/Opin•Measurecurrent•FailIOHtestifthecurrentisgreaterthan+4.5uAorlessthan-4.5uAPassFailGT4.5uA2.0V10nAPMUforceMeasureVss=0VDDmaxILOHVLSICoreAllinputpins=2.3VAlloutputpins=0V/2.3VOFFOFFPre-conditionPattern1/0FailLT-4.5uA“1”DCTest–TestProgramConditionTPHPatternVSIM(V)Vin(other)Vin(DQ0-7)IN