TD-LO13-DR-2006v0T

SemiconductorManufacturingInternationalCorporationDoc.No.:TD-LO13-DR-2006Doc.Title:0.13umLogic1P8MSalicide1.2/1.5vDesignRuleDoc.Rev:0TTechDevRev:0.1PageNo.:1/78TheinformationcontainedhereinistheexclusivepropertyofSMIC,andshallnotbedistributed,reproduced,ordisclosedinwholeorinpartwithoutpriorwrittenpermissionofSMIC.Accordingto:DocumentControlProcedure;AttachmentNo.:QR-QUSM-02-2001-023;Rev.:0DocumentLevel:(ForEngineering&QualityDocument/工程暨品质文件专用)Level1-ManualLevel2–Procedure/SPEC/ReportLevel3-OperationInstructionSecurityLevel:Security1-SMICConfidentialSecurity2-SMICRestrictedSecurity3-SMICInternalDocumentChangeHistoryDoc.Rev.TechDev.Rev.EffectiveDateAuthorChangeDescription0T0.12005-3-10Brandon_LiInitiateSemiconductorManufacturingInternationalCorporationDoc.No.:TD-LO13-DR-2006Doc.Title:0.13umLogic1P8MSalicide1.2/1.5vDesignRuleDoc.Rev:0TTechDevRev:0.1PageNo.:2/78TheinformationcontainedhereinistheexclusivepropertyofSMIC,andshallnotbedistributed,reproduced,ordisclosedinwholeorinpartwithoutpriorwrittenpermissionofSMIC.Accordingto:DocumentControlProcedure;AttachmentNo.:QR-QUSM-02-2001-023;Rev.:01.Title:0.13umLogic1P8MSalicide1.2/1.5vDesignRule2.Purpose:PatternsDesignGuidelinefor0.13umLogicProcess,especiallyforcustomerNewton3.Scope:AllSMICFabs4.Nomenclature:NA5.Reference:NA6.Responsibility:TechnologyDevelopmentCenter7.SubjectContent:SemiconductorManufacturingInternationalCorporationDoc.No.:TD-LO13-DR-2006Doc.Title:0.13umLogic1P8MSalicide1.2/1.5vDesignRuleDoc.Rev:0TTechDevRev:0.1PageNo.:3/78TheinformationcontainedhereinistheexclusivepropertyofSMIC,andshallnotbedistributed,reproduced,ordisclosedinwholeorinpartwithoutpriorwrittenpermissionofSMIC.Accordingto:DocumentControlProcedure;AttachmentNo.:QR-QUSM-02-2001-023;Rev.:0SEMICONDUCTORMANUFACTURINGINTERNATIONALCORPORATION0.13µmLOGIC1P8MSalicide1.2/1.5VforNewtonDesignRulesSMICConfidential–DoNotCopySemiconductorManufacturingInternationalCorporationDoc.No.:TD-LO13-DR-2006Doc.Title:0.13umLogic1P8MSalicide1.2/1.5vDesignRuleDoc.Rev:0TTechDevRev:0.1PageNo.:4/78TheinformationcontainedhereinistheexclusivepropertyofSMIC,andshallnotbedistributed,reproduced,ordisclosedinwholeorinpartwithoutpriorwrittenpermissionofSMIC.Accordingto:DocumentControlProcedure;AttachmentNo.:QR-QUSM-02-2001-023;Rev.:07.UserGuidePartI:DescriptionofSMICMaskLayers5PartII:SuggestionfortheOptimizedCircuitDesign57.1Introduction7.1.1SMICMaskLayerNameMappingTable67.1.2DefinitionofGeometricalPatternsinPhysicalLayout97.2LayoutRuleDescription7.2.1DNW:DeepN-WellRule107.2.2NW:N-WellRule117.2.3NWR:N-WellResistor127.2.4NN:NativeNMOS147.2.5AA:ActiveAreaRule167.2.6DG:DualGateRule187.2.7GT:PolyRule207.2.8NLL:1.2VNLDDImplantationRule227.2.9PLL:1.2VPLDDImplantationRule247.2.10NLH:1.5VNLDDImplantationRule267.2.11PLH:1.5VPLDDImplantationRule287.2.12SN:N+S/DImplantationRule307.2.13SP:P+S/DImplantationRule327.2.14SAB:SalicideBlockRule347.2.15CT:ContactRule367.2.16BEOLdesignrulesummary387.2.17M1:Metal1Rule397.2.18V1:Via1Rule427.2.19Mn:Metaln(n=2,3,4,5,6,7)Rule437.2.20Vn:Vian(n=2,3,4,5,6)Rule467.2.21VT1:TopViaRule487.2.22MT1:TopMetalRule507.2.23VT2:TopViaRule527.2.24MT2:TopMetalRule547.2.25MetalSlotRules567.2.26MetalDummyRules587.2.27CDR:CurrentDensityRule597.2.28MetalFuseRule627.2.29FuseRepairingAlignmentMarkRules647.2.30SealringandGuardRingGuideline667.2.31NCrule717.2.32PCrule737.2.33MVNrule757.2.34MVPrule778.Attachment:N/ASemiconductorManufacturingInternationalCorporationDoc.No.:TD-LO13-DR-2006Doc.Title:0.13umLogic1P8MSalicide1.2/1.5vDesignRuleDoc.Rev:0TTechDevRev:0.1PageNo.:5/78TheinformationcontainedhereinistheexclusivepropertyofSMIC,andshallnotbedistributed,reproduced,ordisclosedinwholeorinpartwithoutpriorwrittenpermissionofSMIC.Accordingto:DocumentControlProcedure;AttachmentNo.:QR-QUSM-02-2001-023;Rev.:07UserGuidePartI:Suggestionfortheoptimizedcircuitdesign7-1NWRTrytoputNWRinsideAAtominimizethedeviationofNWresistance.7-2AATrytoavoidlongnarrowwidthtransistor.ItisrecommendedthatusingAAresistorblocklayer(RESAA)onAAresistor.7-3Poly1)AllgatepolymustbeorthogonaltoAAedge.2)It’snotrecommendedtouse45degreebentpoly.Ifit’spossible,don’tuse45degreebentpolyatall.3)KeepthespaceofpolyonAAlargerthan0.18µm(1.2V)or0.25um(1.5V),theminimumrule,toavoidcurrentcrowdingeffect.4)Drawpolyend-caplargerthan0.18µmtopreventmismatchinlogicoperation5)Forpolyresistor,makesurethepolybecoveredbySABanditisrecommendedthatusingpolyresistorblocklayer(RESP1)onpolyresistor.TheCTareasonpolyresistorneedtobesilicided.7-4SNandSP1)TheSNisrecommendednottobegeneratedbythereversedtoneofSP2)TheSPisrecommendednottobegeneratedbythereversedtoneofSN7-5CT&Via1)Increasemetallineendenclosurewheneverpossible.2)IncreasemetalenclosureasbigaspossibleforthestackedCT/Vias.3)UseredundantCTandViaswheneverpossible.7-6DummyAdddummypatterntomeetminimummetaldensityrequirement;makemetalpatternasuniformaspossibletohelpCMPplanarity.AddslotinsolidwidemetallinetoreduceCMPdishingeffect.7.1Introduction7.1.1SMICmasklayernamemappingtableNoLayerNameDescription10MZeromask2DNWDeepNWell3AAActivear