基于FPGA的FIR数字滤波器的设计

16ISN710071TheDesignofFirDigitalFilterBasedonFPGALiXing,YangJiawei(InformationScienceInstituteofStateLaboratoryofISN,XidianUniversity,Xi´an710071,China)AbstractThepaperpresentsadesignmethodforfirdigitalfilterbasedonFPGA.ThecoefficientquantizationofthefilteriscalculatedandsimulatedusingtheMATLAB,andthefirfilterdescribedbyVHDLissynthesizedandsimulated.Theresultsmeetthedesignrequirements.KeywordsFPGA;FIRdigitalfilter;simulateFPGAFPGAFIRFFTDSPFIR2005-10-25FIR10−≤≤NnZ[1]∑−=−=10)()(NnnZnhZH1nZ−N1ZN1N1ZZ0FIRj(e)dHωFIRjj(e)()enHhnωω−=⋅j(e)dHωj(e)dHω[2]πjjπ1()(e)ed2πnnddHnHωωω−=⋅∫2j(e)dHω)(nHd20067202/200671517FIR)(nh)(nh()dhn)(nhd)(nW[1])()()(nhnWnhd⋅=3481.5dB40dB{h0(k)k=0,1,…,47}σ=200)]()([khkThk∑∞=−−τβ≤0.034FPGAFIR2σ=121M+1*2b2−5Mb45121M+1*2b2−≤9*104−6M=486b=6.3MATLABb≥812bitXilinxISE5.xISEFPGAVHDL[2]FIR1NFIRFIRFIRy(n)=∑−=−−+2/)1(0)()]1()([NiihiNxix7248FIR24DDDDDDDx(n)h(1)h(2)h(0)h(N/2-1)y(n)1−Z1−Z1−Zh(0)h(1)h(2)0y(n)h(N-1)ITAge/Jul.15,200618clkdinVHDLifclk='1'andclk'eventthentap=tap(46downto0)&din;iftap(0)='0'thent(0):=h(0);elset(0):=noth(0)+'1';endif;foriin1to23loopiftap(i)=tap(48-i)theniftap(i)='0'thent(i):=h(i)+h(i);elset(i):=(noth(i)+'1')+(noth(i)+'1');endif;elset(i):=(others='0');endif;endloop;iftap(24)='0'thent(24):=h(24);elset(24):=noth(24)+'1';endif;ISESynplifypro7.3.1RTL3ISEModelSim0101010104un1_tap[21:4]p1.22.un270_clk=tap[45:0]t_21_4[5]01t_21_4[5]p1.21.un259_clkp1.22.un270_clk[45:0]dinclk[22][24]Q[45:0]0[21][44:0]D[45:0]tap[45:0][21:4]clk[45:0][21:4][21:4]un1_tap[21:4]ITAge/Jul.15,200622Rset2.57V40mA5PWM5PWM51540mAPWMIoutPWMPWMPWM2.57V540mA1,.PWM[J].,2004,30(11):5457.2AllenPE,HolbergDR.CMOSAnalogCircuitDesign[M].:,2005:93137.3,.[].:,1998.FIR1,.()[M].:,2001.2,,.FPGA/CPLD—XilinxISE5.X[M].:,2004.3,,.MATLAB5.X[M].:,2001.4,.VHDL[M].:,2004.5,,.[M].:,2004.40mA15mA5mA420420420876878880882884886888890892894/mA/V/mA/mA