SPI数据格式

SynchronousSerialInterface497Jz4755MultimediaApplicationProcessorProgrammingManual,Revision1.0Copyright®2005-2007IngenicSemiconductorCo.,Ltd.Allrightsreserved.23.5DataFormatsFoursignalsareusedtotransferdatabetweentheprocessorandexternalperipheral.TheSSIsupportsthreeformats:MotorolaSPI,TexasInstrumentsSSP,andNationalMicrowire.Althoughtheyhavethesamebasicstructurethethreeformatshavesignificantdifferences,asdescribedbelow.SSI_CE_/SSI_CE2_variesforeachprotocolasfollows:•ForSPIandMicrowireformats,SSI_CE_/SSI_CE2_functionsasachipselecttoenabletheexternaldevice(targetofthetransfer),andisheldactive-lowduringthedatatransfer.•ForSSPformat,thissignalispulsedhighforoneserialbit-clockperiodatthestartofeachframe.SSI_CLKvariesforeachprotocolasfollows:ForMicrowire,bothtransmitandreceivedatasourcesswitchdataonthefallingedgeofSSI_CLK,andsampleincomingdataontherisingedge.ForSSP,transmitandreceivedatasourcesswitchdataontherisingedgeofSSI_CLK,andsampleincomingdataonthefallingedge.ForSPI,theuserhasthechoiceofwhichedgeofSSI_CLKtouseforswitchingoutgoingdata,andforsamplingincomingdata.Inaddition,theusercanmovethephaseofSSI_CLK,shiftingitsactivestateone-halfperiodearlierorlateratthestartandendofaframe.WhileSSPandSPIarefull-duplexprotocols,Microwireusesahalf-duplexmaster-slavemessagingprotocol.Atthestartofaframe,a1or2-bytecontrolmessageistransmittedfromthecontrollertotheperipheral.Theperipheraldoesnotsendanydata.Theperipheralinterpretsthemessageand,ifitisaREADrequest,respondswithrequesteddata,oneclockafterthelastbitoftherequestingmessage.Theserialclock(SSI_CLK)onlytogglesduringanactiveframe.Atothertimesitisheldinaninactiveoridlestate,asdefinedbyitsspecifiedprotocol.23.5.1Motorola’sSPIFormatDetails23.5.1.1GeneralSingleTransferFormatsThefiguresbelowshowthetimingofgeneralsingletransferformat.SynchronousSerialInterface498Jz4755MultimediaApplicationProcessorProgrammingManual,Revision1.0Copyright®2005-2007IngenicSemiconductorCo.,Ltd.Allrightsreserved.Figure23-1SPISingleCharacterTransferFormat(PHA=0)Figure23-2SPISingleCharacterTransferFormat(PHA=1)ForSSICR1.PHA=0,whenSSICR1.TFVCK=B’00,hardwareensuresthefirstclockedgeappearsoneSSI_CLKperiodafterSSI_CE_/SSI_CE2_goesvalid;whenSSICR1.TCKFI=B’00,hardwareensurestheSSI_CE_/SSI_CE2_negatedhalfSSI_CLKperiodafterlastclockchangeedge;whenSSICR1.TFVCK≠B’00orSSICR1.TCKFI≠B’00,1/2/3moreclockcyclesareinserted.ForSSICR1.PHA=1,whenSSICR1.TFVCK=B’00,hardwareensuresthefirstclockedgeappearshalfSSI_CLKperiodafterSSI_CE_/SSI_CE2_goesvalid;whenSSICR1.TCKFI=B’00,hardwareensurestheSSI_CE_/SSI_CE2_negatedoneSSI_CLKperiodafterlastclockchangeedge;whenSSICR1.TFVCK≠B’00orSSICR1.TCKFI≠B’00,1/2/3moreclockcyclesareinserted.MSBMSBLSBLSBSSI_CLK(POL=0)SSI_CLK(POL=1)SSI_CE_/SSI_CE2_(SSICR1.FRMHLn=0)SSI_DTSSI_DRSSI_GPCGPC…………MSBMSBLSBLSBGPCSSI_CLK(POL=0)SSI_CLK(POL=1)SSI_GPCSSI_CE_/SSI_CE2_(SSICR1.FRMHLn=0)SSI_DTSSI_DR…………SynchronousSerialInterface499Jz4755MultimediaApplicationProcessorProgrammingManual,Revision1.0Copyright®2005-2007IngenicSemiconductorCo.,Ltd.Allrightsreserved.DataissampledfromSSI_DRateveryrisingedge(whenPHA=0,POL=0orPHA=1,POL=1)orateveryfallingedge(whenPHA=0,POL=1orPHA=1,POL=0).AccordingtoSPIprotocol,inputdataonSSI_DRshouldbestableateverysampleclockedge.DrivedataontoSSI_DTateveryrisingedge(whenPHA=0,POL=1orPHA=1,POL=0)orateveryfallingedge(whenPHA=0,POL=0orPHA=1,POL=1).23.5.1.2Back-to-BackTransferFormatsFigure23-3SPIBack-to-BackTransferFormatForMotorola’sSPIformattransfersthosecontinuouscharactersareexchangedduringSSI_CE_/SSI_CE2_beingvalid,thetimingisillustratedinthefigure(SSICR1.LFST=0).Back-to-backtransferisperformedastransmit-only/full-duplexoperationwhentransmit-FIFOisnotemptybeforethecompletionofthelastcharacter’stransferorperformedasreceive-onlyoperation.LSBMSBLSBLSBMSBLSBSSI_DTSSI_DRMSBMSBSSI_GPCGPCSSI_CLK(POL=1,PHA=0orPOL=0,PHA=1)SSI_CLK(POL=0,PHA=0orPOL=1,PHA=1)SSI_CE_/SSI_CE2_(SSICR1.FRMHLn=0)……………………SynchronousSerialInterface500Jz4755MultimediaApplicationProcessorProgrammingManual,Revision1.0Copyright®2005-2007IngenicSemiconductorCo.,Ltd.Allrightsreserved.23.5.1.3FrameIntervalModeTransferFormatWheninintervalmode(SSIITR.IVLTM≠‘0’),SSIalwayswaitforanintervaltime(SSIITR.IVLTM),transferfixednumberofcharacters(SSIICR),thenrepeatstheoperation.WhenSSICR0.RFINE=1,iftransmit-FIFOisstillemptyaftertheintervaltime,receive-onlytransferwilloccur.Duringinterval-waittime,SSIstopsSSI_CLK,andwhenSSICR1.ITFRM=0itnegatestheSSI_CE_/SSI_CE2_,whenSSICR1.ITFRM=1itkeepsassertingtheSSI_CE_/SSI_CE2_.Fortransfersfinishedwithtransmit-FIFOempty,iftheSSItransmit-FIFOisemptybeforefixednumberofcharactersbeingloadedtotransfer(SSICR1.UNFINmustbe1),thentheSSIwillsetSSISR.UNDR=1;ifenabled,it’llsendoutaSSIunderruninterrupt.Atthesametime,SSIwillholdtheSSI_CE_/SSI_CE2_andSSI_CLKsignalsatcurrentstatusandwaitforthetransmit-FIFOfilling.TheSSIwillcontinuetransferaftertransmit-FIFObeingfilled.TheSSIalwaysstopsaftercompletionoffixednumberofcharacters’transfer(SSICR1.UNFINmustbe0)withtransmit-FIFOempty.FortransfersfinishedbySSICR0.RFINCbeingvali