EDA设计试题

21，Whichofthefollowingcoreareaswillproducethesmallestdiesize?a)Nop-flippedandseparatedrowsb)Flippedandabuttedrowsc)Flippedandseparatedrowsd)Non-flippedandabuttedrows22，RefertolayoutA&B，whichofthefollowingistrue:A:W/L=2/0.5B:W/L=4/0.25a)BhasthesameareaasAanddoublethedrive.b)BhasdoubletheareaofAandhalfthedrive.c)BhasthesameareaasAandthesamedrive.d)Bhas4XtheareaasAandthesamedrive.e)Bhas4XthedriveasAandthesamearea.23，whichiscorrect?a)Slack=Dataarrivaltime－DataRequiredtimeb)Slack=DataRequiredtime－Dataarrivaltimec)Slack=ClockArrivaltime－Dataarrivaltimed)Slack=ClockRequiredtime－DataRequiredtime24，Inthefollowingfigure,whatisthetotalnumberofpossibledataarrivaltimesforsetup?a)1b)2c)3d)425，Whichwillalwaysresultintheworstslackforsetuptime?a)Thelongestdataarrivaltime.b)Theshortestdataarrivaltime.c)Itisunclearastheslackisafunctionofdataarrivaltimeaswellasdatarequiredtime.26，n-deviceisfasterthanp-devicebecauseReduceAreaa)Holemobilityisgreaterthanelectronmobility.b)Electronmobilityisgreaterthanholemobility.c)ThePthresholdisgreaterthanNthreshold.d)TheNthresholdisgreaterthanPthreshold.e)Noneoftheabove.27，Fora25MHzprocessor,whatisthetimetakenbytheinstructionwhichneeds3clockcyclea)120nanosecsb)120microsecsc)75nanosecsd)75microsecs28，Whichoneiscorrectstatement?a)RTLmodelscanbesimulatedonlyoncyclebasedsimulatorb)Eventdrivensimulatorscansimulatebothsynchronousandasynchronousdesignsc)MulticlockdesignscannotbesimulatedwithEventdrivensimulatorsd)bandc29，Formalanalysismeans:a)Verifyingdesignswithassertionsusingsimulatorsb)Verifyingdesignsonlywithassertionsstaticallyc)AnalyzingfunctionalcoveragegeneratedfromtheassertionIPsd)aandc30，WhichlanguagesupportsobjectorientedprogrammingandgoodforRTLverification?a)C++b)VerilogwithVPIc)SystemVerilogd)bandc31.Whatisthedifferencebetweenlogicandbittypes?(1%)a)logicis2state,bitis4stateb)Thereisnodifferencec)logicis4state,bitis2stated)noneoftheabove32.HowdoyouspecifysignaldirectioninaSystemVeriloginterface?(1%)a)throughclockingblocksb)Throughcrossmodulereferencec)Throughmodportsd)Noneoftheabove33.HowdoIcreateavariablesharedbyallobjectsofaclass,butnotmakeaglobal?(1%)a)declareitasautomaticb)declareitinthetopscopec)declareitassharedd)declareitasstatic34.HowdoIsharecodebetweenclasses?(1%)a)Instantiateaclasswithinanotherclassb)Inheritfromoneclasstoanother(inheritance/derivation)c)alloftheaboved)Noneoftheabove35.Whatisthefinalvalueoft1.dataandt2.datainthiscode?(1%)classThing;intdata;endclassThingt1,t2;initialbegint1=new();t1.data=1;t2.data=2;t2=t1;t1.data=5;enda)t1.data=5,t2.data=5b)t2getsusedbeforenew()iscalled.Nullobjectaccess!c)t1.data=5,t2.data=2;d)Noneoftheabove36.WriteaconstraintforthevariableQthatpicksavalueof0,for75%ofthetimeand1~3fortherest?(1%)a)constraintc{Qdist{0:=75,[1:3]:=25};}b)constraintc{Q4;Q=0;}c)constraintc{Q4;Q=0;Q%2dist{0:=75,1:=25};}d)constraintc{Q4;Q=0;Q%3dist{0:=25,1:=25,2:=25,3:=75};}37.Whatarethepossiblevaluesthatxandywilltakewhenthefollowingclassisrandomized(1%)classE;randbit[15:0]x[10],y[10];constraintsize_cons{foreach(x[i]){x[i]0;x[i]y[i];foreach(y[i])y[i]inside{[1:9]};}}endclassa}xin[0,9],yin[0,9]b)xin[1,9],yin[1,9]c)xin[1,9],yin[2,10]d)xin[1,8],yin[2,9]38.Whatisthefinalvalueoft1.dataandt2.datainthiscode?(1.0%)classThing;intdata;endclassThingt1,t2;initialbegint1=new();t1.data=1;t2.data=2;t2=t1;t1.data=5;enda)t1.data=5,t2.data=5b)t2getsusedbeforenew()iscalled.Nullobjectaccess!c)t1.data=5,t2.data=2;d)Noneoftheabove39.ThenewinternSmartAssertcannotwritesimpleassertions.Hewrote:(a##1(!b[*0:$]##1b)[*3:5]##1C)Whiletheassertionworkscorrectly,canyouhelphimwriteitinasimplifiedform?PleasechooseonecorrectanswerfromA),B),C)andD):(1.0%)A)propertyabc_sequence_with_!b_random_space_between;@(posedgeclk)$rose(a)##1b|-b[*3:5]##1c;endproperty:abc_sequence_with_!b_random_space_between;B)propertyabc_sequence_with_!b_random_space_between;@(posedgeclk)a##1b[=3:5]##1c;endproperty:abc_sequence_with_!b_random_space_between;C)propertyabc_sequence_with_!b_random_space_between;@(posedgeclk)a##1!b[*0:$]##1b[*3:5]##1c;endproperty:abc_sequence_with_!b_random_space_between;D)propertyabc_sequence_with_!b_random_space_between;@(posedgeclk)a##1b[-3:5]##1c;endproperty:acb_sequence_with_!b_random_space_between;40.Considerabusprotocolthatincludestheproperty“anewbuscyclemaynotstartfor2clockcyclesafteranabortcycleoccurs.”Thispropertycouldbecodedasbelow.PleasechooseonecorrectanswerfromA),B),C)andD).(1.0%)A）propertywait_after_abort;@(posedgeclk)wait（abort_cycle）##2!cycle_start;endproperty:wait_after_abort;B）propertywait_after_abort;@(posedgeclk)while(abort_cycle)##2Not(cycle_start);endproperty:wait_after_abortC）propertywait_after_abort;@(posedgeclk)abort_cycle|=!cycle_start[*2];endproperty:wait_after_abortD）propertywait_after_abort;@(posedgeclk)abort_cycle|-Not(##2cycle_start);endproperty:wait_after_abort41.考虑以下两个逻辑表达式f和g,Considerthefollowinglogicexpressionsforfandg:ƒ=x12x5x+1x2x4x5x+x1x2x4x5+1x2xx34x+x12xx3x5+2x3xx45x+x1x2x3x45xg=2xx34x+2x3x4x5x+x1x3x45x+x12xx45x+x1x3x4x5+1x2x3x5x+x1x23xx4x5证明这两个表达式相等或者不相等。