半导体工艺-复旦大学-蒋玉龙-Chapter-5

Chapter5DeviceScaling-downPrinciplesandLimitationsOutlineI.MOSdevicedownscalingprinciplesII.VerificationofScalingRelationshipofDeviceParametersIII.PracticalScalingforMOSdevicesIV.BipolarDeviceScalingV.TwoapproachesofdeepsubmicronCMOSDeviceScaling9High-performanceandLow-powerVI.SemiconductorTechnologyRoadmapbasedonscaling-downprincipleVII.DeviceScalingLimitationVIII.ExplorationofthenanometerCMOStechnologyI.MOSdevicedownscalingprinciples‹Deviceminiaturizationleadstodeviceperformanceandproductionimprovementinallaspect:function,speed,powerdissipation,reliability,costandproductivity¾MOSdevicescaling-downprinciplesbyDennardetal(IBM)(IEEEJ.SolidStateCircuits,SC-9,5,256,(1974))1.R.Dennardetal,DesignofIon-ImplantedMOSFET’swithVerySmallPhysicalDimensions,IEEEJ.ofSolid-StateCircuits,Vol.SC-9,No.5,P.256(1974)2B.Davari,R.DennardandG.Shahidi,CMOSScalingforHighPerformanceandLowPower–TheNext10Years,ProceedingsoftheIEEE83,4,595(1995)‹ConstantelectricfieldscalingofMOSIC*Electricfieldwillremainconstanteverywhereinthedevice*NoincreaseinpowerdensityonchipwhileincreasingthedeviceintegrationdensityDeviceParametersScalingFactorsLateralDimensions(Lg,Wg)1/k(k1)JunctionDepth(xj)1/kOxideThickness(tox)1/kSubstrateDoping(Ns)kPowerSupplyVoltage(VDD)1/kThresholdVoltage(VT)1/kCurrent(I)1/kInversion-layerchargedensity(Qi)1Channelresistance(Rch)1Capacitance(C=εLgWg/tox)1/kCircuitDelayTime(τ=CΔV/I)1/kPowerDissipation1/k2PowerDissipationDensity1Speed-PowerProduct1/k3ChipIntegrationDensityk2TransistorPerformanceICcircuitPerformanceDeviceDesignII.VerificationofScalingRelationshipofDeviceParameters(1)DepletionwidthinSiofpnjunctionandMOSinterfaceOriginaldevice:Scaleddevice:2/1)(2⎥⎦⎤⎢⎣⎡+=ASidqNVWψεkWqkNkVWdASid≈⎥⎦⎤⎢⎣⎡+=2/1)/(2'ψεpotentialsurfaceorinBuilt−−−−−ψ(Underthecondition:ψVDD)(notvalidatsmallVDD)(2)Thresholdvoltage{}effBOXOXSmsTQQtVV−−+Ψ+=ε()[]{}()[]{}kVkVqkNQktVVqNQtVVTSubSASieffOXOXSmsSubSASieffOXOXSmsT≈+Ψ+−+Ψ+=+Ψ+−+Ψ+=2/12/1/'2'''''2''''εεεε(Assume:1.(Vms+Ψs)issmall;2.ByadjustingVSub,(ψS+VSub)scaledownbyk)Vms—Workfunctiondifference(=(Wm-Ws)/q)ψS—Surfacepotential(=2kT/q×lnNA/nI)Qeff—EffectiveoxidechargedensityVSub—Substratebias(3)DrainCurrentInlinearregion:DDTGoxoxeffDVVVVLWtI]2[−−=εμ;kIkVkVkVkVkLkWktIDDDTGoxoxeffD≈−−=/]2//[///'εμInsaturationregion:2)(21TGoxoxeffDsatVVLWtI−≈εμkIkVVLWtkVVkLkWktIDsatTGoxoxeffTGoxoxeffDsat=−=−=22')(21)(21///εμεμVD--Drainvoltage;--Gatevoltageμeff--Surfaceeffectivecarriermobility;(infact,)*Currentdensityremainsconstant''//DDDIIkIWWkW==effeffμμ≈'↓↑⇒effANμ(4)MaximumoperatingfrequencyofMOSTransistor(fT)Inputcurrent:GoGGDGSinvWLCjvCCji~)(~)(~ωω≈+≈Outputcurrent:Gmoutvgi~~≈GoGminoutTvWLCjvgiiatf~)(~~~:ω=⇒=∴DonconstVmVCLWgregionlinearinDμ==|,Q∴222)(2LVWLCgfgWLCfDnomTmoTπμππ==⇒=),(22εμεππεμnDnTvLVLvLf====TTkfkLvf==/2'π(5)Switchingpower)()()(22'2''''wattskPkfkVkACfVACPacToToac===Switchingenergy)()(21)(21'322'''jouleskEkVkACVACEoo===III.PracticalScalingforMOSdevices‹ConstantVoltageScaling(CV)‹Quasi-ConstantVoltageScaling(QCV)kkkαParameterQCVCVGeneralizedScalingChannelLength1/k1/k1/kChannelWidth1/k1/k1/kOxideThickness1/k1/k1/21/kJunctionDepth1/k1/k1/kDopingLevelkkαk(α1)PowerSupply1/k1/21α/kFeaturesize(μm)Supplyvoltage（V）Gateoxidethickness(nm)Oxidefield(MV/cm)25351.41.25252.00.85182.80.53.3122.80.353.3103.30.252.573.6IV.BipolarDeviceScaling‹MoreComplicated:TheirverticalstructureandoperationalprincipledonotallowscalingsimilartoMOS¾VT~Constant¾HighertransconductanceMainParametersforBipolar--JunctionCapacitance--BaseTransitTime--SeriesResistance--RCTimeConstantDeviceDimensions(L,W,d)1/kVoltage(V)1Current(I)1/k2Capacitance(C)1/k2DelayTime(CΔV/I)1Power(VI)1/k2PowerDensity1SpeedPowerProduct1/k2V.TwoapproachesofdeepsubmicronCMOSDeviceScaling−High-performanceandLow-power‹High-performanceapproach¾Max.speed¾Adequatelongtermdevicereliability¾Lowleakage¾Highdrivecurrent¾NoGIDLbyband-to-bandtunnelinginthedrainregionduetohighelectricfield(GIDL:GateInducedDrainLeakage)PracticalScalingofSupplyVoltageandGateOxideElectricalField‹Low-powervoltageapproach¾Reducedpowersupplyvoltage¾Maintainapowerdensityas1umCMOS(ClosetoCEscaling)¾Gatedelay~1.5xofhigh-performancedeviceLate80’s19921995199820012004VDD(V)(High-PF)55/3.33.3/2.52.5/1.81.51.2VDD(V)(Low-PW)-3.3/2.52.5/1.51.5/1.21.01.0Lith.Res.(μm)General1.250.80.50.350.250.18Gatelevel(μm)-0.60.350.250.180.13Channellength(μm)0.90.6/0.450.35/0.250.2/0.150.10.07Tox(nm)2315/129/76/53.52.5Relativedensity1.02.56.312.82548RelativespeedHighPF1.01.4/2.02.7/3.44.2/5.17.29.6LowPW-1.0/1.62.0/2.43.2/3.54.57.2HP&LPCMOSExsample:FujitsuRoadmapforHP(CS)&LPCMOSHP&LPCMOSExample:Fujitsu65nmCMOS-HP(CS200)&LP(CS200A)65nmCMOS:HPvsLPExample:Fujitsu-HP(CS200)&LP(CS200A)HPLP‹Gatelength30nm50nm‹CoreVDD1.0V1.2V‹Gateoxidethickness(physical)1.1nm1.7nm‹GateelectrodeNiSi/Poly-SiCoSi2/Poly-Si‹Source/drainelectrodeNiSiCoSi2‹Interconnects11-Cu+1-Al‹Metal1pitch0.18µm‹Inter-leveldielectricPorousULK(k=2.25)‹DraincurrentenhancementAdvancedstresscontrolVISemiconductorTechnologyRoadmapbasedonscaling-downprinciple‹MOSdevicescalingsince197