FPGA全局时钟约束(Xilinx)

©2003Xilinx,Inc.AllRightsReservedGlobalTimingConstraints7-3©2003Xilinx,Inc.AllRightsReserved••ConstraintsEditorGlobalTimingConstraints7-4©2003Xilinx,Inc.AllRightsReserved••••GlobalTimingConstraints7-5©2003Xilinx,Inc.AllRightsReserved•–•––XilinxConstraintsEditorGlobalTimingConstraints7-6©2003Xilinx,Inc.AllRightsReserved•––50MHzGlobalTimingConstraints7-7©2003Xilinx,Inc.AllRightsReserved••60MHz•GlobalTimingConstraints7-8©2003Xilinx,Inc.AllRightsReserved•–––•–GlobalTimingConstraints7-9©2003Xilinx,Inc.AllRightsReserved•–I/O–RAM•–1–2•–I/OGlobalTimingConstraints7-10©2003Xilinx,Inc.AllRightsReservedGlobalTimingConstraints7-11©2003Xilinx,Inc.AllRightsReserved•••=BUFGCLKADATAOUT2OUT1QFLOP3DQFLOP1DQFLOP5DQFLOP4DBUS[7..0]CDATAQFLOP2DGlobalTimingConstraints7-12©2003Xilinx,Inc.AllRightsReserved•–FLOP1,FLOP2,FLOP3,FLOP4,FLOP5•–BUFGCLKADATAOUT2OUT1QFLOP3DQFLOP1DQFLOP5DQFLOP4DBUS[7..0]CDATAQFLOP2DGlobalTimingConstraints7-13©2003Xilinx,Inc.AllRightsReserved••••GlobalTimingConstraints7-14©2003Xilinx,Inc.AllRightsReservedPERIOD•PERIOD•PERIODBUFGCLKADATAOUT2OUT1QFLOP3DQFLOP1DQFLOP5DQFLOP4DBUS[7..0]CDATAQFLOP2DGlobalTimingConstraints7-15©2003Xilinx,Inc.AllRightsReserved•PERIOD––––•–50-%CLK–10nsPERIOD–FF2CLK10ns50%=5nsPERIODBUFGINVCLKFF1FF2GlobalTimingConstraints7-16©2003Xilinx,Inc.AllRightsReserved••–PERIOD–OFFSETIN•–PERIOD–OFFSETIN–OFFSETOUTGlobalTimingConstraints7-17©2003Xilinx,Inc.AllRightsReservedPad-to-Pad••I/OGlobalTimingConstraints7-18©2003Xilinx,Inc.AllRightsReservedGlobalTimingConstraints7-19©2003Xilinx,Inc.AllRightsReserved•CLK1PERIOD•DQDQGLATCHFLOPCLK2RAMOUT2OUT1CLK1BUFGDBUFGPADAPADBPADCGlobalTimingConstraints7-20©2003Xilinx,Inc.AllRightsReserved•CLK1PERIOD–FLOPLATCH•–PADCOUT2DQDQGLATCHFLOPCLK2RAMOUT2OUT1CLK1BUFGDBUFGPADAPADBPADCGlobalTimingConstraints7-21©2003Xilinx,Inc.AllRightsReservedOFFSET•OFFSET–OFFSETIN–OFFSETOUTBUFGCLKADATAOUT2OUT1QFLOPDQFLOPDQFLOPDQFLOPDBUS[7..0]CDATAQFLOPDOFFSETINOFFSETOUTGlobalTimingConstraints7-22©2003Xilinx,Inc.AllRightsReservedOFFSET•OFFSET–––•OFFSET–PERIODGlobalTimingConstraints7-23©2003Xilinx,Inc.AllRightsReserved•OFFSET–OFFSETIN=T_data_In-T_clk_In–OFFSETOUT=T_data_Out+T_clk_OutPage3OutClkT_data_InT_data_OutT_clk_InOFFSET-OUTOFFSET-INInT_clk_OutGlobalTimingConstraints7-24©2003Xilinx,Inc.AllRightsReservedGlobalTimingConstraints7-25©2003Xilinx,Inc.AllRightsReservedRAMOUT2OUT1CLKQDQDGLATCHFLOPBUFGPADAPADBPADC•OFFSETINOFFSETOUTGlobalTimingConstraints7-26©2003Xilinx,Inc.AllRightsReserved•OFFSETINOFFSETOUT–OFFSETIN:PADAFLOPPADBRAM–OFFSETOUT:LATCHOUT1,LATCHOUT2,RAMOUT1RAMOUT2OUT1CLKQDQDGLATCHFLOPBUFGPADAPADBPADCGlobalTimingConstraints7-27©2003Xilinx,Inc.AllRightsReserved••••GlobalTimingConstraints7-28©2003Xilinx,Inc.AllRightsReservedConstraintsEditor•ProcessesforSourceUserConstraints•CreateTimingConstraintsGlobalTimingConstraints7-29©2003Xilinx,Inc.AllRightsReservedPERIODPad-To-Pad•PERIODpad-to-padGlobaltab•PERIOD•Pad-to-Pad•DeleteGlobalTimingConstraints7-30©2003Xilinx,Inc.AllRightsReservedPERIOD•TIMESPEC•––•PERIOD––•GlobalTimingConstraints7-31©2003Xilinx,Inc.AllRightsReservedOFFSET•OFFSETIN/OUTGlobalPadtosetup=OFFSETINClocktopad=OFFSETOUTGlobalTimingConstraints7-32©2003Xilinx,Inc.AllRightsReserved••••GlobalTimingConstraints7-33©2003Xilinx,Inc.AllRightsReserved•100MHzConstraintsEditor–3ns2nsGlobalTimingConstraints7-34©2003Xilinx,Inc.AllRightsReserved•100MHzConstraintsEditor•PERIOD=10ns,OFFSETIN=7nsOFFSETOUT=8ns3ns2ns10ns7ns8nsUpstreamDeviceDownstreamDeviceGlobalTimingConstraints7-35©2003Xilinx,Inc.AllRightsReserved••PERIOD•OFFSET•ConstraintsEditorGlobalTimingConstraints7-36©2003Xilinx,Inc.AllRightsReserved•–DocumentationÆTechnicalTipsÆTiming&ConstraintsÆGettingStartedÆTheTimingPresentation•–ProblemSolver