Verilog入门教程

1VerilogHDL1.1VerilogHDLVerilogHDLVerilogHDLVerilogHDLVerilogHDLVerilogCVerilogHDLVerilogHDL,1.2VerilogHDL1983GatewayDesignAutomationVerilogHDLVerilogHDL1990OpenVerilogInternationalOVIVerilog1992OVIVerilogOVIIEEEVerilog1995IEEEIEEEStd13641995Verilog1.3Verilog•andornand•UDP•pmosnmosGatewayDesignAutomationCadenceDesignSystems•••VerilogHDL•••VerilogHDLIEEE•VerilogEDA•VerilogHDLPLIPLIVerilog•RTL•••VerilogHDL•VerilogHDLRTL••1-1VerilogHDL•VerilogHDL&|••••1VerilogHDLIEEE2VerilogHDL3VerilogHDL2VerilogHDL1-1RTL45VerilogHDL6VerilogHDL7VerilogHDL8UDP910132HDLHDL2.1Verilog;;modulemodule_name(port_list);Declarations:reg,wire,parameter,input,output,inout,function,task,...Statements:InitialstatementAlwaysstatementModuleinstantiationGateinstantiationUDPinstantiationContinuousassignmentendmodule,2-1moduleHalfAdder(A,B,Sum,Carry);inputA,B;outputSum,Carry;assign#2Sum=A^B;assign#5Carry=A&B;endmoduleHalfAdder4:ABSumCarry,1,,2-1AB1)2)3)4)VerilogHDL2.2VerilogHDLassign#2Sum=A^B;#22:`timescale1ns/100ps1ns100ps(0.1ns),#22ns,VerilogHDLIEEEVerilogHDL2.3:assign[delay]LHS_net=RHS_expression;,,,02-22-42-22-42HDL5`timescale1ns/1nsmoduleDecoder2x4(A,B,EN,Z);inputA,B,EN;output[0:3]Z;wireAbar,Bbar;assign#1Abar=~A;//1assign#1Bbar=~B;//2assign#2Z[0]=~(Abar&Bbar&EN);//3assign#2Z[1]=~(Abar&B&EN);//4assign#2Z[2]=~(A&Bbar&EN);//5assign#2Z[3]=~(A&B&EN);//6endmodule`,`timescale1ns1ns#1#21ns2nsDecoder2x4314AbarBbar()62-3EN5ns,3456ENZ[0]7ns0A15ns,15656Z[0]Z[1]5Z[2]17ns01Abar16nsAbarZ[0]18ns1,2-32.41)initial6VerilogHDL2)always,always0always12-4moduleFA_Seq(A,B,Cin,Sum,Cout);inputA,B,Cin;outputSum,Cout;regSum,Cout;regT1,T2,T3;always@(AorBorCin)beginSum=(A^B)^Cin;T1=A&Cin;T2=B&Cin;T3=A&B;Cout=(T1|T2)|T3;endendmoduleFA_SeqSumCoutT1T2T3always,reg(reg)always(@)(begin-end)ABCinABCinalwaysABCin:1):2):Sum=(A^B)^Cin;#4T1=A&Cin;44Sum=#3(A^B)^Cin;,3Sum0always8initial`timescale1ns/1ns2HDL72-41moduleTest(Pop,Pid);outputPop,Pid;regPop,Pid;initialbeginPop=0;//1Pid=0;//2Pop=#51;//3Pid=#31;//4Pop=#60;//5Pid=#20;//6endendmodule2-5initial0ns,initial120ns0,Pop5ns45ns,Pid8nsPop14ns0Pid16ns6initial8initial2-5Test2.5VerilogHDL:1)()2)()3)()4)()2-4moduleFA_Str(A,B,Cin,Sum,Cout);inputA,B,Cin;outputSum,Cout;wireS1,T1,T2,T3;xorX1(S1,A,B),X2(Sum,S1,Cin);and8VerilogHDLA1(T3,A,B),A2(T2,B,Cin),A3(T1,A,Cin),orO1(Cout,T1,T2,T3);endmodulexorandorS1T1T2T3,xorandorX1X2A1S1xorX1ABX14412-64moduleFourBitFA(FA,FB,FCin,FSum,FCout);parameterSIZE=4;input[SIZE:1]FA,FB;output[SIZE:1]FSuminputFCin;inputFCout;wire[1:SIZE1]FTemp;FA_StrFA1(.A(FA[1]),.B(FB[1]),.Cin(FCin),.Sum(FSum[1]),.Cout(FTemp[2])),FA2(.A(FA[2]),.B(FB[2]),.Cin(FTemp[1]),.Sum(FSum[2]),.Cout(FTemp[2])),FA3(FA[3],FB[3],FTemp[2],FSum[3],FTemp[3],FA4(FA[4],FB[4],FTemp[3],FSum[4],FCout);endmodule4FA1FA2.port_name(net_name)FA3FA4FA4FA[4]FA_StrAFB[4]FA_StrB2-642.62HDL9alwaysinitialalwaysinitialalwaysinitial1moduleFA_Mix(A,B,Cin,Sum,Cout);inputA,B,Cin;outputSum,Cout;regCout;regT1,T2,T3;wireS1;xorX1(S1,A,B);//always@(AorBorCin)begin//alwaysT1=A&Cin;T2=B&Cin;T3=A&B;Cout=(T1|T2)|T3;endassignSum=S1^Cin;//endmoduleABABCinalwaysS1Cin2.7VerilogHDLTop2.3FA_Seqtimescale1ns/1nsmoduleTop;//regPA,PB,PCi;wirePCo,PSum;//FA_SeqF1(PA,PB,PCi,PSum,PCo);//initialbegin:ONLYONCEreg[3:0]Pal;//4,Pal8for(Pal=0;Pal8;Pal=Pal+1)10VerilogHDLbegin{PA,PB,PCi}=Pal;#5$display(PA,PB,PCi=%b%b%b,PA,PB,PCi,:::PCo,PSum=%b%b,PCo,PSum);endendendmodulePAFA_SeqAPBFA_SeqBforPAPBPCifor$display$display$display55Palbegin-end,ONLY_ONCE2-7PA,PB,PCi=000:::PCo,PSum=00PA,PB,PCi=001:::PCo,PSum=01PA,PB,PCi=010:::PCo,PSum=01PA,PB,PCi=011:::PCo,PSum=10PA,PB,PCi=100:::PCo,PSum=01PA,PB,PCi=101:::PCo,PSum=10PA,PB,PCi=110:::PCo,PSum=10PA,PB,PCi=111:::PCo,PSum=112-7TopRS_FF2-8`timescale10ns/1nsmoduleRS_FF(Q,Qbar,R,S);outputQ,Qbar;inputR,S;nand#1(Q,R,Qbar);2HDL112-8nand#1(Qbar,S,Q,);//endmodulemoduleTest;regTS,TR;wireTQ,TQb;//RS_FFNSTA(.Q(TQ),.S(TS),.R(TR),.Qbar(TQb));////initialbegin:TR=0;TS=0;#5TS=1;#5TS=0;TR=1;#5TS=1;TR=0;#5TS=0;#5TR=1;end//initial$monitor(Attime%t,,$time,TR=%b,TS=%b,TQ=%b,TQb=%b,TR,TS,TQ,TQb);endmoduleRS_FF1RQbarTQT+1TestRS_FFTSTR$monitor2-9`timescale2-9Test12VerilogHDLAttime0,TR=0,TS=0,TQ=x,TQb=xAttime10,TR=0,TS=0,TQ=1,TQb=1Attime50,TR=0,TS=1,TQ=1,TQb=1Attime60,TR=0,TS=1,TQ=1,TQb=0Attime100,TR=1,TS=0,TQ=1,TQb=0Attime110,TR=1,TS=0,TQ=1,TQb=1Attime120,TR=1,TS=0,TQ=0,TQb=1Attime150,TR=0,TS=1,TQ=0,TQb=1Attime160,TR=0,TS=1,TQ=1,TQb=1Attime170,TR=0,TS=1,TQ=1,TQb=0Attime200,TR=0,TS=0,TQ=1,TQb=0Attime210,TR=0,TS=0,TQ=1,TQb=1Attime250,TR=1,TS=0,TQ=1,TQb=1Attime260,TR=1,TS=0,TQ=0,TQb=112`timescale342-415initialalways62-10BullsEye2-10BullsEye72-22-482.3Decode2x49VerilogHDL10112-11VerilogHDL12assignReset=#2^WriteBus;2HDL132-113VerilogVerilogHDLVerilog3.1VerilogHDL(identifier)$()CountCOUNT//Count_R1_D2R56_68FIVE$(escapedidentifier)\()\7400\.*.$\{******}\~Q\OutGateOutGate\OutGateOutGateVerilogHDLAalways()ALWAYS()\initialinitial3.2VerilogHDL/*:*///:3.3VerilogHDLVerilogHDL3Verilog15initialbeginTop=3b001;#2Top=3b011;end:initialbeginTop=3b001;#2Top=3b011;end3.4$00$display(Hi,youhavereachedLTtoda