Leakage aware dynamic voltage scaling for real-tim

LeakageAwareDynamicVoltageScalingforRealTimeEmbeddedSystemsRavindraJejurikarCristianoPereiraRajeshK.GuptaCenterforEmbeddedComputerSystems,DepartmentofInformationandComputerScience,UniversityofCaliforniaatIrvine,Irvine,CA92697E-mail:[e-mail],fcpereira,[e-mail]#03-35November30,2003AbstractTraditionally,dynamicvoltagescalingtechniqueshavebeendesignedtominimizethedynamicpowerconsumption,whichhasbeenthedominantfactor.Asthetechnologyscales,leakagecurrentiscon-tributingtosignificantenergyconsumption.Inthispaper,weproposetaskschedulingtechniquesthattakeleakageintoaccounttominimizethetotalenergyconsumption.Wecomputeanoperatingpointcalledthecriticalspeedwhichminimizesthedynamicandleakageenergyconsumptionperunitwork.Theleakageenergydominateswhenoperatingatspeedslowerthanthecriticalspeedanditisenergyefficienttoexecutefasterandshutdownthesystem.Duetothetimeandenergycostassociatedwithshutdown,longershutdownintervalsarebetter.Toaddressthisissue,wealsopresentaschedulingpro-crastinationscheme,whichdelaystaskexecutiontoextendsleepintervals.Oursimulationexperimentsshowonanaverage20%energygainsoveraleakageobliviousdynamicvoltagescalingandthepro-crastinationschemeincreasesthegainstoupto35%.Ourschedulingschemeextendsthesleepintervalstoupto5timeswhilemeetingalltimingrequirements.1Contents1Introduction12PowerModel23CriticalSpeed34RealTimeScheduling54.1Background.........................................54.2DVSandCriticalSpeed...................................64.3ShutdownOverhead.....................................64.4ProcrastinationAlgorithm.................................64.4.1ComputingProcrastinationInterval........................74.4.2Algorithm......................................75Experiments95.1ShutdownOverhead.....................................105.2EnergyConsumption....................................106ConclusionsandFutureWork12AProofs162ListofFigures1Powerconsumptionof0:07μmtechnologyforCrusoeprocessor:PDCistheleakagepower,PACisthedynamicpowerandPonistheintrinsicpowerconsumptioninonstate.42EnergyperCyclefor0:07μmtechnologyfortheCrusoeprocessor:EACistheswitchingenergy,EDCistheleakageenergyandEonistheintrinsicenergytokeeptheprocessoron.53ProcrastinationAlgorithm.................................84Energyconsumptionnormalizedtono-DVS........................115Comparisonof#wakeupsandidleenergyofCS-DVS-PnormalizedtoCS-DVS.....126ComparisonofaveragesleepandidleintervalofCS-DVS-PnormalizedtoCS-DVS...13ListofTables10:07μmtechnologyconstants................................331IntroductionPowermanagementisofprimaryimportanceintheoperationofembeddedsystems,whichcanbeat-tributedtolongerbatterylife,reliabilityandpackagingcosts.Powerconsumptionofadeviceisbroadlyclassifiedasdynamicpowerconsumptionwhicharisesduetoswitchingenergyandstaticpowercon-sumptionwhichispresentevenwhennologicoperationsareperformed.CMOShasemergedasadominanttechnologybecauseofitslowstaticpowerconsumption.CMOSdevicescalingtrends,drivenbytheneedforfasterdevicesandhighertransistordensities,showa30%decreaseinthedevicedimen-sionswitheachtechnologygeneration[5].Constantelectricfieldscalingallowsaproportionalreductionofsupplyvoltage.Assupplyvoltageisreduced,thethresholdvoltage(Vth)mustbeproportionatelyre-ducedtomaintainthedesiredperformance(delay)improvements.Thisreductionofthresholdvoltageresultsinanexponentialincreaseinthesubthresholdleakagecurrent[6],leadingtolargerstandbycurrent.LeakagecurrentinCMOScircuitscontributetoasignificantportionofthetotalpowerconsumptionandisbecominganincreasingconcern.Thesubthresholdleakagecurrentis0:01μA=μmforthe130nmandisprojectedtobe3μA=μmforthe45nmtechnology[1].Afivefoldincreaseintheleakagepowerispredictedwitheachtechnologygeneration[5].Thestaticpowerconsumptioniscomparabletothedynamicpowerdissipationandprojectedtosurpassitifmeasuresarenottakentominimizeleakagecurrent[9].Furthermore,leakagehasanadverseeffectwiththeincreaseintemperature[29].Toaddressthisissue,effortsatprocess,circuitdesignandmicro-architecturelevelaremadetomin-imizeleakagepower.Theexponentiallydependenceofsubthresholdleakagecurrentonthethresholdvoltagehasledtothresholdvoltagescaling.Scalingthethresholdvoltagebycontrollingthebodybiasvoltage[23,21]hasbeenproposedtominimizeleakage.MultithresholdCMOS(MTCMOS)[7]isapopulartechniquetoreducestandbycurrent.Othertechniquessuchasinputvectorcontrol[14]andpowersupplygating[22]havebeenproposed.Athigherlevelsofabstraction,recentworkshavefo-cusedonminimizingtheleakageofcomponentssuchascache.Techniqueslikecachedecay[11]andturningoffcachelines[10]reducehaveshowneffectiveresultsinreducingcacheleakage.ClockgatingtechniquesarealsousedtocontrolleakageinSystemsonChip(SoC).TheIBMPowerPC405LP[8]implementsclockgatingattheIPcoreandregisterlevel.TheIntelPXA[12]familyprocessorsalsosupportfinegranularityclockgatingtoexploitthefactthatnotallsystemtransistorsareusedatthesametime.Thechipaggressivelyshutsdownelementsoftheprocessorwhichareidlebygatingthemoffordisablingtheirinput.Processorssupportvariousshutdownmodetosavepower